Index Any RegisterĪll registers( Input Register and Output Registers) can be indexed using Loop Counter Register (only constant registers could be indexed in earlier versions.) The 3_0 vertex shader model (vs_3_0) expands on the features of vs_2_0 with more powerful register indexing, a set of simplified output registers, the ability to sample a texture in a vertex shader, and the ability to control the rate at which shader inputs are initialized. Each register that is used needs to be declared using the dcl instruction and a semantic (for example, dcl_color0 o0.xyzw).

The vertex shader output register types have been collapsed into twelve registers (see Output Registers).

Match Semantics on vs_3_0 and ps_3_0 Shaders.

Attributes with D3DDECLUSAGE_TEXCOORD and usage index from 0 to 15 are interpolated in wrap mode when the corresponding D3DRS_WRAP* is set. See Match Semantics on vs 3.0 and ps 3.0 Shaders.Īdditional wrap mode render states have been added to cover the possibility of additional texture coordinates in this new scheme. The semantics are used to map the vertex shader outputs to the pixel shader inputs, similar to the way the vertex declaration is mapped to the vertex shader input registers and previous shader models. The semantics used on vertex shader outputs must be used on pixel shader inputs. In addition, if you are using a software-only vs_3_0 shader with a previous pixel shader version, the vertex shader can only use output semantics that are compatible with flexible vertex format (FVF) codes. The only exception is that software-only vs_3_0 shaders may be used with any pixel shader version. These changes make it possible to simplify drivers and the runtime. If you are implementing shaders in hardware, you may not use vs_3_0 or ps_3_0 with any other shader versions, and you may not use either shader type with the fixed function pipeline.

Vertex shaders and pixel shaders are simplified considerably from earlier shader versions.

Shader 3.0 download windows 10